#***************************************************
#		global variable
#***************************************************
# pll clock
set sclk *pll|altpll_component|auto_generated|pll1|clk\[0\]

#***************************************************
#			clock
#***************************************************
# osc
create_clock \
    -period 40 \
    -name clk_in \
    [get_ports sclkin]

# gp rxc
create_clock \
    -period 8 \
    -name gp0_rxc \
    [get_ports gp0_rxc]

create_clock \
    -period 8 \
    -name gp1_rxc \
    [get_ports gp1_rxc]


# pll clock
derive_pll_clocks
derive_clock_uncertainty

# logic clock
create_generated_clock -name rgmii_p0_out_clock -source [get_pins {comm_top|phy_interface|trans_io_a|oddr_1bit_txc|ALTDDIO_OUT_component|auto_generated|dataout[0]}] [get_ports gp0_txc]
create_generated_clock -name rgmii_p1_out_clock -source [get_pins {comm_top|phy_interface|trans_io_b|oddr_1bit_txc|ALTDDIO_OUT_component|auto_generated|dataout[0]}] [get_ports gp1_txc]

#***************************************************
#		false path
#***************************************************
# cross clock domain
set_clock_groups \
    -asynchronous \
    -group "$sclk" \
    -group "clk_in" \
    -group "gp0_rxc" \
    -group "gp1_rxc"

#***************************************************
#			PHY
#***************************************************
set_input_delay -clock [get_clocks {gp0_rxc}] -max 3 [get_ports {gp0_rxd[*]}] -add_delay
set_input_delay -clock [get_clocks {gp0_rxc}] -max 3 [get_ports {gp0_rxdv}] -add_delay
set_input_delay -clock [get_clocks {gp0_rxc}] -max 3 [get_ports {gp0_rxd[*]}] -clock_fall -add_delay
set_input_delay -clock [get_clocks {gp0_rxc}] -max 3 [get_ports {gp0_rxdv}] -clock_fall -add_delay
set_input_delay -clock [get_clocks {gp0_rxc}] -min 1 [get_ports {gp0_rxd[*]}] -add_delay
set_input_delay -clock [get_clocks {gp0_rxc}] -min 1 [get_ports {gp0_rxdv}] -add_delay
set_input_delay -clock [get_clocks {gp0_rxc}] -min 1 [get_ports {gp0_rxd[*]}] -clock_fall -add_delay
set_input_delay -clock [get_clocks {gp0_rxc}] -min 1 [get_ports {gp0_rxdv}] -clock_fall -add_delay

set_input_delay -clock [get_clocks {gp1_rxc}] -max 3 [get_ports {gp1_rxd[*]}] -add_delay
set_input_delay -clock [get_clocks {gp1_rxc}] -max 3 [get_ports {gp1_rxdv}] -add_delay
set_input_delay -clock [get_clocks {gp1_rxc}] -max 3 [get_ports {gp1_rxd[*]}] -clock_fall -add_delay
set_input_delay -clock [get_clocks {gp1_rxc}] -max 3 [get_ports {gp1_rxdv}] -clock_fall -add_delay
set_input_delay -clock [get_clocks {gp1_rxc}] -min 1 [get_ports {gp1_rxd[*]}] -add_delay
set_input_delay -clock [get_clocks {gp1_rxc}] -min 1 [get_ports {gp1_rxdv}] -add_delay
set_input_delay -clock [get_clocks {gp1_rxc}] -min 1 [get_ports {gp1_rxd[*]}] -clock_fall -add_delay
set_input_delay -clock [get_clocks {gp1_rxc}] -min 1 [get_ports {gp1_rxdv}] -clock_fall -add_delay

set_false_path -setup -rise_from [get_clocks {*clk_gen_inst|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {rgmii_p0_out_clock}]
set_false_path -setup -fall_from [get_clocks {*clk_gen_inst|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {rgmii_p0_out_clock}]
set_false_path -hold -rise_from [get_clocks {*clk_gen_inst|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {rgmii_p0_out_clock}]
set_false_path -hold -fall_from [get_clocks {*clk_gen_inst|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {rgmii_p0_out_clock}]

set_false_path -setup -rise_from [get_clocks {*clk_gen_inst|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {rgmii_p1_out_clock}]
set_false_path -setup -fall_from [get_clocks {*clk_gen_inst|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {rgmii_p1_out_clock}]
set_false_path -hold -rise_from [get_clocks {*clk_gen_inst|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {rgmii_p1_out_clock}]
set_false_path -hold -fall_from [get_clocks {*clk_gen_inst|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {rgmii_p1_out_clock}]

set_output_delay -clock [get_clocks {rgmii_p0_out_clock}] -max 9  [get_ports {gp0_txen}] -add_delay
set_output_delay -clock [get_clocks {rgmii_p0_out_clock}] -max 9  [get_ports {gp0_txen}] -clock_fall -add_delay
set_output_delay -clock [get_clocks {rgmii_p0_out_clock}] -max 9  [get_ports {gp0_txd[*]}] -add_delay
set_output_delay -clock [get_clocks {rgmii_p0_out_clock}] -max 9  [get_ports {gp0_txd[*]}] -clock_fall -add_delay
set_output_delay -clock [get_clocks {rgmii_p0_out_clock}] -min -1 [get_ports {gp0_txen}] -add_delay
set_output_delay -clock [get_clocks {rgmii_p0_out_clock}] -min -1 [get_ports {gp0_txen}] -clock_fall -add_delay
set_output_delay -clock [get_clocks {rgmii_p0_out_clock}] -min -1 [get_ports {gp0_txd[*]}] -add_delay
set_output_delay -clock [get_clocks {rgmii_p0_out_clock}] -min -1 [get_ports {gp0_txd[*]}] -clock_fall -add_delay

set_output_delay -clock [get_clocks {rgmii_p1_out_clock}] -max 9  [get_ports {gp1_txen}] -add_delay
set_output_delay -clock [get_clocks {rgmii_p1_out_clock}] -max 9  [get_ports {gp1_txen}] -clock_fall -add_delay
set_output_delay -clock [get_clocks {rgmii_p1_out_clock}] -max 9  [get_ports {gp1_txd[*]}] -add_delay
set_output_delay -clock [get_clocks {rgmii_p1_out_clock}] -max 9  [get_ports {gp1_txd[*]}] -clock_fall -add_delay
set_output_delay -clock [get_clocks {rgmii_p1_out_clock}] -min -1 [get_ports {gp1_txen}] -add_delay
set_output_delay -clock [get_clocks {rgmii_p1_out_clock}] -min -1 [get_ports {gp1_txen}] -clock_fall -add_delay
set_output_delay -clock [get_clocks {rgmii_p1_out_clock}] -min -1 [get_ports {gp1_txd[*]}] -add_delay
set_output_delay -clock [get_clocks {rgmii_p1_out_clock}] -min -1 [get_ports {gp1_txd[*]}] -clock_fall -add_delay
